Computer systems typically contain many low cost peripheral chips such as e.g., sensors. These chips are often attached to the main processor through a low pin count bus such as e.g. I2C. While such a low pin count bus brings the benefit of reduced overall costs, it comes at the cost of reduced functionality. Functionalities not available in the I2C protocol are the detection of presence and/or power status of a remote device.
State of the art is communication (e.g. via I2C) between a host computer and remote devices connected via a bus protocol. Then the problem exists that a failure detection is needed for the communication. A prior art solution is to use an additional sense line between the host computer and the device.
As mentioned above a situation is assumed where a host computer is connected to a remote device through a low-pin count bus, e.g. I2C. The host computer runs software that accesses the remote device. In this setup, the remote device can assume four states, three of which are error conditions:
Scenario a): The bus system between the host system and the remote device is disconnected.
Scenario b): The bus system between the host system and the remote device is connected, but the remote device is not supplied with power.
Scenario c): The bus system between the host system and the remote device is connected, the remote device is supplied with power but not responding, i.e. remote device is broken.
Scenario d): The bus system between the host system and the remote device is connected; the remote device is supplied with power and is responding and/or operational.
It should be noted that scenario (d) can always be detected by the fact that the remote device is responding to requests of the host system. However, depending on the protocol of the low-pin count bus, a control unit on the host system cannot distinguish between scenarios a) through c). Hence, the control unit can only detect that a remote device is working (d) or a remote device is not working. In the latter case, any of the error scenarios a) through c) could have occurred.
When a host system needs to precisely detect and distinguish between more scenarios, state-of-the art approaches shown in FIGS. 3 and 4 add another dedicated signal line as sense line SSL to the bus lines SCL, SDA.
The algorithm for the state-of-the art approach shown in FIG. 3 works as follows: The dedicated sense line SSL is pulled low on the host system side by a high impedance pull-down resistor RHS0. When a remote device is attached, the sense line SSL is pulled high by the remote device through a relatively low impedance pull-up resistor RRS1. The host system can then distinguish the scenarios a) to d) as follows:                Scenario a): The sensing signal on sense line SSL is low.        Scenario b): The sensing signal on sense line SSL is low.        Scenario c): The sensing signal on sense line SSL is high, but the remote device is not responding.        Scenario d): The sensing signal on sense line SSL is high and the remote device is responding.        
However, it is still unable to distinguish between scenario a) or b).
The algorithm for the state-of-the art approach shown in FIG. 4 works as follows: The dedicated sense line SSL is pulled high on the host system side by a high impedance pull-up resistor RHS1. When a remote device is attached, the sense line SSL is pulled low by the remote device through a relatively low impedance pull-down resistor RRS0. The host system can then distinguish the scenarios a) to d) as follows:                Scenario a): The sensing signal on the sense line SSL is high.        Scenario b): The sensing signal on the sense line SSL is low, but the remote device is not responding.        Scenario c): The sensing signal on the sense line SSL is low, but the remote device is not responding.        Scenario d): The sensing signal is low and the remote device is responding.        
However, it is still unable to distinguish between situation (b) or (c).
The drawback of these approaches is the additional sense line and the increased signal count resulting in higher complexity and overall system cost.
In the Patent Application Publication US 2006/0095629 A1 “SYSTEM, METHOD AND STORAGE MEDIUM FOR PROVIDING A SERVICE INTERFACE TO A MEMORY SYSTEM” by Gower et al. a cascaded interconnect system for providing a service interface to a memory system, is disclosed. The cascaded interconnect system includes a master service interface module, a service interface bus, and one or more slave service interface modules. The master service interface module and the slave interface modules are cascade interconnected via the service interface bus. Each slave service interface module is in communication with a corresponding memory module for providing a service to the memory module. An exemplary embodiment of the disclosed system includes two parallel FSI modules connected in a cascaded fashion to memory modules. The FSI modules are located on FRU service processors that are located on FSP cards. Connected to each clock wire is a ground resistor termination device, as well as a pull up resistor termination device. The ground resistor termination device, as well as the pull up resistor termination device, improve electrical performance and support a plug detection capability. The values of the pull up resistor termination device and the ground resistor termination device on the FSI data signal are chosen such that when a memory module is plugged in, a logic level of “1” can be detected. When a memory module is not plugged in, a logic level of “0” can be detected.